As memory devices, such as DRAMs, are designed to operate at higher speeds and to have larger storage capacities, their integration densities have generally increased while their design rules have decreased. Horizontal gaps between individual devices in the memories, such as between gates or word lines, have generally reduced in proportion to the decreasing design rules. Moreover, the gap between devices may be further reduced when spacers are formed between the devices. As the gaps between devices become increasingly narrow, defects, such as poor contact filling or misalignment, may occur.
For example, bit lines may be insulated from gates by filling the gaps between the gates with an insulating layer. With decreased design rules, the gaps between the gates may become sufficiently narrow, such that the insulating layer does not completely fill the gaps and voids result. Filling defects may become particularly common when the design rules are reduced to about 0.14 μm or less. While the width of the gates and/or the thickness of spacers may be reduced to increase the gaps between the gates, the operational characteristics of the memory device, such as the refresh characteristics, may deteriorate.